基于混合硬件/软件的以加速器为中心的异构架构研究

发布时间：2024-02-24 09:28

　　嵌入式系统已经成为人们日常生活中不可或缺的一部分。智能手机,高清电视,洗衣机和汽车牵引力控制系统不仅使生活更舒适,而且使生活更安全。低成本,高性能和高能效的需求已经成为系统设计的关键,为了实现这些需求,以加速器为中心的异构计算成为有效利用硬件的最佳方式。本论文研究了高性能和高能效嵌入式系统的两种设计方法。第一种方法是基于应用剖析来定制处理器架构。第二种方法是设计专用加速器,将其集成到处理器的数据路径,以增强性能。第一种方法涉及到FlexCore处理器中的指令解压缩器的实现以及压缩和解压缩方案的分析。指令解压缩器由VHDL设计和实现,并使用Cadence RTL编译器进行了综合。针对指令解压缩器的硬件实现,本文分析了压缩方案中不同参数的影响。由于节省了内存占用,指令解压缩器大大提高了 FlexCore的性能。然后,本文利用两种类型的加法器电路,纹波进位加法器(RCA)和Sklansky型加法器(SKL),实现了基本算术逻辑单元(ALU)。本文在专用集成电路(ASIC)平台上,使用了 VHDL和标准元件设计了 ALU。综合结果表明,ALU-RCA的面积变化比ALU-SKL更快,因为ALU-...

【文章页数】：174 页

【学位级别】：博士

【文章目录】：
摘要
Abstract
Chapter 1 Introduction
    1.1 Background and Related Work
    1.2 Problem Statement
    1.3 Thesis Outline
Chapter 2 Optimization of Core Processor Architecture
    2.1 Instruction Decompressor Design
        2.1.1 FlexCore Processor Architecture
        2.1.2 Flexible Datapath Interconnect
        2.1.3 The FlexSoC Framework
        2.1.4 Existing Compression Schemes
        2.1.5 Implementation of Compression scheme
        2.1.6 Instruction Decompressor
        2.1.7 Implementation of Instruction Decompressor
        2.1.8 Discussion on Synthesis Results
    2.2 Arithmetic Logic Unit Design
        2.2.1 ALU Design- Verification
        2.2.2 ALU Design- Basic Synthesis
        2.2.3 ALU Design- Design Respin and Power analysis
        2.2.4 ALU Design- Place and Route
    2.3 Conclusion
Chapter 3 Application Specific Accelerator Design
    3.1 CORDIC Accelerator Design
        3.1.1 Standard CORDIC Algorithm
        3.1.2 Hardware Mapping of Standard CORDIC
        3.1.3 Standard CORDIC Hardware Accelerator
        3.1.4 Modified CORDIC Algorithm
        3.1.5 Modified CORDIC Hardware Accelerator
    3.2 CRC Accelerator Design
        3.2.1 CRC Computation Techniques
        3.2.2 CRC Accelerator Implementation
        3.2.3 Integration of CRC Accelerator with MicroBlaze
    3.3 Viterbi Accelerator Design
        3.3.1 Convolutional Encoding and Viterbi Decoding
        3.3.2 Initial Viterbi Decoder
        3.3.3 Mixed HW/SW Viterbi Accelerator
        3.3.4 Integration of Viterbi Accelerator with MicroBlaze
    3.4 Conclusion
Chapter 4 Heterogeneous Architectures
    4.1 Digital Hearing Aid
        4.1.1 Types of Hearing Aids
        4.1.2 Signal Processing Techniques
        4.1.3 Basic Description of System
        4.1.4 Mixed Hardware/Software Implementation
        4.1.5 Hardware Implementation
    4.2 Distance and Speed Measurement
        4.2.1 Software Implementation
        4.2.2 Mixed Hardware/Software Implementation
        4.2.3 Hardware Implementation
        4.2.4 ASIC Implementation
    4.3 Conclusion
Chapter 5 Conclusion and Future Directions
    5.1 Summary
    5.2 Future Directions
References
Acknowledgements
List of Publications



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